触发器

汽车逻辑器件同步接口逻辑器件控制逻辑器件开关二极管 N沟道MOS管三级管

74AHC374; 74AHCT374

Octal D-type flip-flop; positive-edge trigger; 3-state

应用领域

The 74AHC374; 74AHCT374 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC374; 74AHCT374 comprises eight D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock input (CP) and an output enable input (OE) are common to all flip-flops.

The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition.

When OE is LOW the content of the eight flip-flops is available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

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产品详情

特性

Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than VCC
Common 3-state output enable input
Input levels:

For 74AHC374: CMOS level
For 74AHCT374: TTL level

ESD protection:

HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V

Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74AHC374D	Production	2.0 - 5.5	CMOS	± 8	4.4	185	low	-40~125	84	27.0	61	SO20
74AHC374PW	Production	2.0 - 5.5	CMOS	± 8	4.4	185	low	-40~125	100	4.5	44.5	TSSOP20
74AHCT374D	Production	4.5 - 5.5	TTL	± 8	4.3	140	low	-40~125	84	27.0	61	SO20
74AHCT374PW	Production	4.5 - 5.5	TTL	± 8	4.3	140	low	-40~125	100	4.5	44.5	TSSOP20