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Octal D-type flip-flop; positive-edge trigger; 3-state
The 74AHC574; 74AHCT574 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74AHC574; 74AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.
The 74AHC574; 74AHCT574 is functionally identical to the 74AHC564; 74AHCT564, but has non-inverting outputs. The 74AHC574; 74AHCT574 is functionally identical to the 74AHC374; 74AHCT374, but has a
Balanced propagation delays
All inputs have a Schmitt-trigger action
3-state non-inverting outputs for bus orientated applications
8-bit positive, edge-triggered register
Independent register and 3-state buffer operation
Common 3-state output enable input
For 74AHC574 only: operates with CMOS input levels
For 74AHCT574 only: operates with TTL input levels
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
| Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC574BQ | Production | 2.0 - 5.5 | CMOS | ± 8 | 4.4 | 130 | low | -40~125 | 77 | 8.1 | 48 | DHVQFN20 |
| 74AHC574D | Production | 2.0 - 5.5 | CMOS | ± 8 | 4.4 | 130 | low | -40~125 | 84 | 26.4 | 60 | SO20 |
| 74AHC574PW | Production | 2.0 - 5.5 | CMOS | ± 8 | 4.4 | 130 | low | -40~125 | 100 | 4.4 | 44 | TSSOP20 |
| 74AHCT574BQ | Production | 4.5 - 5.5 | TTL | ± 8 | 4.4 | 130 | low | -40~125 | 77 | 8.1 | 48 | DHVQFN20 |
| 74AHCT574D | Production | 4.5 - 5.5 | TTL | ± 8 | 4.4 | 130 | low | -40~125 | 84 | 26.4 | 60 | SO20 |
| 74AHCT574PW | Production | 4.5 - 5.5 | TTL | ± 8 | 4.4 | 130 | low | -40~125 | 100 | 4.4 | 44 | TSSOP20 |
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