74ALVCH16374

2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

应用领域

The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down..

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产品详情

特性

Wide supply voltage range from 1.2 V to 3.6 V
Complies with JEDEC standards:

JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)

CMOS low power dissipation
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple VCC and GND pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Output drive capability 50 Ω transmission lines at 85 °C
IOFF circuitry provides partial Power-down mode operation
Current drive ±24 mA at VCC = 3.0 V
ESD protection:

HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V

Specified from -40 °C to +85 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74ALVCH16374DGG	Production	1.2 - 3.6	TTL	± 24	2.3	350	low	-40~85	82	1.8	35	TSSOP48

触发器

74ALVCH16374

应用领域

特性

参数类型