触发器

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74HC107; 74HCT107

Dual JK flip-flop with reset; negative-edge trigger

应用领域

The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC.

产品详情

特性

  • Wide supply voltage range from 2.0 V to 6.0 V

  • CMOS low power dissipation

  • High noise immunity

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Complies with JEDEC standards:

    • JESD8C (2.7 V to 3.6 V)

    • JESD7A (2.0 V to 6.0 V)

  • Input levels:

    • The 74HC107: CMOS levels

    • The 74HCT107: TTL levels

  • ESD protection:

    • HBM JESD22-A114F exceeds 2000 V

    • MM JESD22-A115-A exceeds 200 V

  • Specified from -40 °C to +85 °C and from -40 °C to +125 °C


参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74HC107DProduction2.0 - 6.0CMOS± 5.21678low-40~125876.545SO14
74HC107PWProduction2.0 - 6.0CMOS± 5.21678low-40~1251273.151.4TSSOP14
74HCT107DProduction4.5 - 5.5TTL± 41673low-40~125876.545SO14