![[pics:title]](/static/upload/image/20230301/1677646214552460.png)
8-bit shift register with output register
The 74AHC594-Q100; 74AHCT594-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC594-Q100; 74AHCT594-Q100 is an 8-bit, non-inverting, serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Separate clocks (SHCP and STCP) and direct overriding clears (SHR and STR) are provided on both the shift and storage registers. A serial output (Q7S) is provided for cascading purposes.
Both the shift and storage register clocks are positive-edge triggered. If the user wishes to connect both clocks together, the shift register will always be one count pulse ahead of the storage register.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 5.5 V
Balanced propagation delays
All inputs have Schmitt-trigger action
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
8-bit serial-in, parallel-out shift register with storage
Independent direct overriding clears on shift and storage registers
Independent clocks for shift and storage registers
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Input levels:
For 74AHC594-Q100: CMOS level
For 74AHCT594-Q100: TTL level
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
Serial-to parallel data conversion
Remote control holding register
| Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC594BQ-Q100 | Production | 2.0 - 5.5 | CMOS | ± 8 | 4.1 | 160 | low | -40~125 | 91 | 12.3 | 60 | DHVQFN16 |
| 74AHC594D-Q100 | Production | 2.0 - 5.5 | CMOS | ± 8 | 4.1 | 160 | low | -40~125 | 90 | 8.6 | 49 | SO16 |
| 74AHC594PW-Q100 | Production | 2.0 - 5.5 | CMOS | ± 8 | 4.1 | 160 | low | -40~125 | 123 | 4.1 | 52.2 | TSSOP16 |
| 74AHCT594BQ-Q100 | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 160 | low | -40~125 | 91 | 12.3 | 60 | DHVQFN16 |
| 74AHCT594D-Q100 | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 160 | low | -40~125 | 90 | 8.6 | 49 | SO16 |
| 74AHCT594PW-Q100 | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 160 | low | -40~125 | 123 | 4.1 | 52.2 | TSSOP16 |
陈先生：13823795018
咨询热线：0755-29834675
Copyright © 2015-2022 深圳瑞天微科技有限公司版权所有 粤ICP备2022109263号
