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8-bit serial-in/serial-out or parallel-out shift register with output latches
The 74AHC595-Q100; 74AHCT595-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The 74AHCT595-Q100 features TTL compatible inputs. Both 74AHC595-Q100 and 74AHCT595-Q100 inputs ar
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 5.5 V
Balanced propagation delays
All inputs have Schmitt trigger action
Overvoltage tolerant inputs to 5.5 V
High noise immunity
CMOS low power dissipation
Input levels:
The 74AHC595-Q100 operates with CMOS input levels
The 74AHCT595-Q100 operates with TTL input levels
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
Serial-to-parallel data conversion
Remote control holding register
| Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC595BQ-Q100 | Production | 2.0 - 5.5 | CMOS | ± 8 | 4 | 170 | low | -40~125 | 90 | 11.8 | 59 | DHVQFN16 |
| 74AHC595D-Q100 | Production | 2.0 - 5.5 | CMOS | ± 8 | 4 | 170 | low | -40~125 | 90 | 8.3 | 49 | SO16 |
| 74AHC595PW-Q100 | Production | 2.0 - 5.5 | CMOS | ± 8 | 4 | 170 | low | -40~125 | 122 | 3.9 | 51.4 | TSSOP16 |
| 74AHCT595BQ-Q100 | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 170 | low | -40~125 | 90 | 11.8 | 59 | DHVQFN16 |
| 74AHCT595D-Q100 | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 170 | low | -40~125 | 90 | 8.3 | 49 | SO16 |
| 74AHCT595PW-Q100 | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 170 | low | -40~125 | 122 | 3.9 | 51.4 | TSSOP16 |
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