触发器/锁存器/寄存器

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74HC109-Q100; 74HCT109-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

应用领域

The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual nJ and nK inputs. It has clock (nCP) inputs, set (nSD) and reset (nRD) inputs and complementary nQ and nQ outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The nJ and nK inputs control the state changes of the flip-flops as described in the mode select function table. The nJ and nK inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the nJ and nK inputs together. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grad

产品详情

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Input levels:

    • For 74HC109-Q100: CMOS level

    • For 74HCT109-Q100: TTL level

  • J and K inputs for easy D-type flip-flop

  • Toggle flip-flop or "do nothing" mode

  • Specified in compliance with JEDEC standard no. 7A

  • ESD protection:

    • MIL-STD-883, method 3015 exceeds 2000 V

    • HBM JESD22-A114F exceeds 2000 V

    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)


参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74HC109D-Q100Production2.0 - 6.0CMOS± 5.21575low-40~125866.644SO16
74HCT109D-Q100Production4.5 - 5.5TTL± 41761low-40~125866.644SO16
74HCT109PW-Q100Production4.5 - 5.5TTL± 41761low-40~1251193.248.1TSSOP16