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Octal D-type transparent latch; 3-state
The 74HC373-Q100; 74HCT373-Q100 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
Input levels:
For 74HC373-Q100: CMOS level
For 74HCT373-Q100: TTL level
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
| Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC373BQ-Q100 | Production | 2.0 - 6.0 | CMOS | ± 7.8 | 12 | 8 | low | -40~125 | 78 | 9.1 | 50 | DHVQFN20 |
| 74HC373D-Q100 | Production | 2.0 - 6.0 | CMOS | ± 7.8 | 12 | 8 | low | -40~125 | 85 | 27.3 | 61 | SO20 |
| 74HC373PW-Q100 | Production | 2.0 - 6.0 | CMOS | ± 7.8 | 12 | 8 | low | -40~125 | 100 | 4.6 | 44.7 | TSSOP20 |
| 74HCT373BQ-Q100 | Production | 4.5 - 5.5 | TTL | ± 6 | 14 | 8 | low | -40~125 | 78 | 9.1 | 50 | DHVQFN20 |
| 74HCT373D-Q100 | Production | 4.5 - 5.5 | TTL | ± 6 | 14 | 8 | low | -40~125 | 85 | 27.3 | 61 | SO20 |
| 74HCT373PW-Q100 | Production | 4.5 - 5.5 | TTL | ± 6 | 14 | 8 | low | -40~125 | 100 | 4.6 | 44.7 | TSSOP20 |
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