16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
The 74LVC16373A-Q100 and 74LVCH16373A-Q100 are 16-bit D-type transparent latches with 3-state outputs. The devices can be used as two 8-bit transparent latches or a single 16-bit transparent latch. The devices feature two latch enables (1LE and 2LE) and two output enables (1OE and 2OE), each controlling 8-bits. When nLE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When nLE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of nLE. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
MULTIBYTE flow-through standard pinout architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16373A-Q100 only)
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V
Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
---|---|---|---|---|---|---|---|---|---|---|---|
74LVC16373ADGG-Q100 | Production | 1.2 - 3.6 | TTL | ± 24 | 3 | low | -40~125 | 82 | 2.0 | 37 | TSSOP48 |
74LVC16373ADGV-Q100 | Production | 1.2 - 3.6 | TTL | ± 24 | 3 | low | -40~125 | 82 | 2.0 | 37 | TVSOP48 |
74LVCH16373ADGG-Q100 | Production | 1.2 - 3.6 | TTL | ± 24 | 3 | low | -40~125 | 82 | 2.0 | 37 | TSSOP48 |
74LVCH16373ADGV-Q100 | Production | 1.2 - 3.6 | TTL | ± 24 | 3 | low | -40~125 | 82 | 2.0 | 37 | TVSOP48 |