74LVC1G79-Q100

Single D-type flip-flop; positive-edge trigger

应用领域

The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

Information on the data input is transferred to the Q-output on the LOW-to-HIGH transition of the clock pulse. The D-input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 1.65 V to 5.5 V
High noise immunity
Complies with JEDEC standard:

JESD8B/JESD36 (2.7 V to 3.6 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-7 (1.65 V to 1.95 V)

ESD protection:

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
HBM JESD22-A114F exceeds 2000 V
MIL-STD-883, method 3015 exceeds 2000 V

±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Power dissipation considerations Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74LVC1G79GV-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 32	2.2	450	low	-40~125	270	63.3	169	TSOP5
74LVC1G79GW-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 32	2.2	450	low	-40~125	311	80.9	181	TSSOP5

触发器/锁存器/寄存器

74LVC1G79-Q100

应用领域

特性

参数类型