74LVC374A-Q100

Octal D-type flip-flop; 5 V tolerant inputs/outputs; positive-edge trigger; 3-state

应用领域

The 74LVC374A-Q100 is an octal positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electr

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 1.2 V to 3.6 V
Overvoltage tolerant inputs to 5.5 V
CMOS low power dissipation
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
8-bit positive edge-triggered register
Independent register and 3-state buffer operation
Complies with JEDEC standard:

JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)

ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74LVC374ABQ-Q100	Production	1.2 - 3.6	CMOS/LVTTL	± 24	2.7	100	low	-40~125	78	9.0	49	DHVQFN20
74LVC374AD-Q100	Production	1.2 - 3.6	CMOS/LVTTL	± 24	2.7	100	low	-40~125	85	27.1	61	SO20
74LVC374APW-Q100	Production	1.2 - 3.6	CMOS/LVTTL	± 24	2.7	100	low	-40~125	101	4.6	45	TSSOP20

触发器/锁存器/寄存器

74LVC374A-Q100

应用领域

特性

参数类型