多谐振荡器

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74LVC1G123

Single retriggerable monostable multivibrator; Schmitttrigger inputs

应用领域

The 74LVC1G123 is a single retriggerable monostable multivibrator with Schmitt trigger inputs. Output pulse width is controlled by three methods:

The basic pulse is programmed by selection of an external resistor (REXT) and capacitor (CEXT).
Once triggered, the basic output pulse width may be extended by retriggering the gated active LOW-going edge input (A) or the active HIGH-going edge input (B). By repeating this process, the output pulse period (Q = HIGH) can be made as long as desired. Alternatively an output delay can be terminated at any time by a LOW-going edge on input CLR, which also inhibits the triggering.
An internal connection from CLR to the input gates makes it possible to trigger the circuit by a HIGH-going signal at input CLR.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment. Schmitt trigger inputs, makes the circuit highly tolerant to slower input ri

产品详情

特性

  • Wide supply voltage range from 1.65 V to 5.5 V

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • DC triggered from active HIGH or active LOW inputs

  • Retriggerable for very long pulses up to 100 % duty factor

  • Direct reset terminates output pulse

  • Schmitt trigger on all inputs

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V)

  • Power-on-reset on outputs

  • Latch-up performance exceeds 100 mA

  • Direct interface with TTL levels

  • Inputs accept voltages up to 5.5 V

  • ESD protection:

    • HBM JESD22-A114F exceeds 2000 V

    • MM JESD22-A115-A exceeds 200 V

    • CDM JESD22-C101E exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C


参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G123DCProduction1.65 - 5.5CMOS/LVTTL± 323.5low-40~12520334.0113VSSOP8
74LVC1G123DPProduction1.65 - 5.5CMOS/LVTTL± 323.5low-40~12521419.8105TSSOP8
74LVC1G123GNProduction1.65 - 5.5CMOS/LVTTL± 323.5low-40~12523710.5147XSON8
74LVC1G123GSProduction1.65 - 5.5CMOS/LVTTL± 323.5low-40~12527510.7145XSON8
74LVC1G123GTProduction1.65 - 5.5CMOS/LVTTL± 323.5low-40~1253266.1156XSON8