74HC4060-Q100; 74HCT4060-Q100

14-stage binary ripple counter with oscillator

应用领域

The 74HC4060-Q100; 74HCT4060-Q100 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered parallel outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC) floating. The counter advances on the HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs LOW, independent of the other input conditions. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
All active components on chip
RC or crystal oscillator configuration
Input levels:

For 74HC4060-Q100: CMOS level
For 74HCT4060-Q100: TTL level

Complies with JEDEC standards:

JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)

ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

目标应用

Control counters
Timers
Frequency dividers
Time-delay circuits

参数类型

Type number	Product status	VCC (V)	Output drive capability (mA)	Logic switching levels	tpd (ns)	fmax (MHz)	Power dissipation considerations Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74HC4060BQ-Q100	Production	2.0 - 6.0	± 5.2	CMOS	31	87	low	-40~125	82	6.2	50	DHVQFN16
74HC4060D-Q100	Production	2.0 - 6.0	± 5.2	CMOS	31	87	low	-40~125	82	4.7	40	SO16
74HC4060PW-Q100	Production	2.0 - 6.0	± 5.2	CMOS	31	87	low	-40~125	114	2.1	42.5	TSSOP16
74HCT4060BQ-Q100	Production	4.5 - 5.5	± 4	TTL	31	88	low	-40~125	82	6.2	50	DHVQFN16
74HCT4060D-Q100	Production	4.5 - 5.5	± 4	TTL	31	88	low	-40~125	80	4.3	38.9	SO16

计数器/分频器

74HC4060-Q100; 74HCT4060-Q100

应用领域

特性

目标应用

参数类型