![[pics:title]](/static/upload/image/20230301/1677646214552460.png)
14-stage binary counter
The HEF4020B is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from -40 °C to +85 °C
Wide supply voltage range from 3.0 V to 15.0 V
CMOS low power dissipation
High noise immunity
High speed operation
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Complies with JEDEC standard JESD 13-B
| Type number | Product status | VCC (V) | Output drive capability (mA) | Logic switching levels | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| HEF4020BT-Q100 | Production | 4.5 - 15.5 | ± 2.4 | CMOS | 35 | 30 | medium | -40~85 | 56 | 1.0 | 13 | SO16 |
陈先生：13823795018
咨询热线：0755-29834675
Copyright © 2015-2022 深圳瑞天微科技有限公司版权所有 粤ICP备2022109263号
