74LV4060

14-stage binary ripple counter with oscillator

应用领域

The 74LV4060 is a 14-stage ripple-carry counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered parallel outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case, keep the oscillator pins (RTC and CTC) floating. The counter advances on the HIGH-to-LOW transition of RS. A HIGH level on MR clears all counter stages and forces all outputs LOW, independent of the other input conditions. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.

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产品详情

特性

Wide supply voltage range from 1.0 V to 5.5 V
Optimized for low voltage applications from 1.0 V to 3.6 V
CMOS low power dissipation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 °C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 °C
All active components on-chip
RC or crystal oscillator configuration
Complies with JEDEC standard no. 7A
ESD protection:

HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115A exceeds 200 V

目标应用

Control counters
Timers
Frequency dividers
Time-delay circuits

参数类型

Type number	Product status	VCC (V)	Output drive capability (mA)	Logic switching levels	tpd (ns)	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74LV4060D	Production	1.0 - 5.5	± 6	TTL	29	low	-40~125	80	4.3	38.9	SO16
74LV4060PW	Production	1.0 - 5.5	± 6	TTL	29	low	-40~125	114	2.1	42.5	TSSOP16

计数器/分频器

74LV4060

应用领域

特性

目标应用

参数类型