计数器/分频器

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HEF4017B

5-stage Johnson decade counter

应用领域

The HEF4017B is a 5-stage Johnson decade counter with ten spike-free decoded active HIGH outputs (Q0 to Q9), an active LOW carry output from the most significant flip-flop (Q5-9), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).

The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH.

When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8, and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0, CP1).

Automatic counter code correction is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.

Schmitt trigger action makes the clock inputs highly tolerant of slower rise and fall times.

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产品详情

特性

  • Automatic counter correction

  • Tolerant of slow clock rise and fall times

  • Fully static operation

  • 5 V, 10 V, and 15 V parametric ratings

  • Standardized symmetrical output characteristics

  • Specified from -40 °C to +125 °C

  • Complies with JEDEC standard JESD 13-B


参数类型

Type numberProduct statusVCC (V)Output drive capability (mA)Logic switching levelstpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
HEF4017BTProduction4.5 - 15± 2.4CMOS4030medium-40~85919.350.8SO16