74HC4020; 74HCT4020

14-stage binary ripple counter

应用领域

The 74HC4020; 74HCT4020 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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产品详情

特性

Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:

JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)

Input levels:

For 74HC4020: CMOS level
For 74HCT4020: TTL level

ESD protection:

HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V

Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

目标应用

Frequency dividing circuits
Time delay circuits
Control counters

参数类型

Type number	Product status	VCC (V)	Output drive capability (mA)	Logic switching levels	tpd (ns)	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74HC4020BQ	Production	2.0 - 6.0	± 5.2	CMOS	11	low	-40~125	83	7.0	51	DHVQFN16
74HC4020D	Production	2.0 - 6.0	± 5.2	CMOS	11	low	-40~125	83	5.2	41	SO16
74HC4020PW	Production	2.0 - 6.0	± 5.2	CMOS	11	low	-40~125	115	2.3	43.8	TSSOP16
74HCT4020BQ	Production	4.5 - 5.5	± 4	TTL	15	low	-40~125	83	7.0	51	DHVQFN16
74HCT4020D	Production	4.5 - 5.5	± 4	TTL	15	low	-40~125	81	4.8	40.2	SO16
74HCT4020PW	Production	4.5 - 5.5	± 4	TTL	15	low	-40~125	115	2.3	43.8	TSSOP16

计数器/分频器

74HC4020; 74HCT4020

应用领域

特性

目标应用

参数类型