计数器/分频器

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74HC590

8-bit binary counter with output register; 3-state

应用领域

The 74HC590 is an 8-bit binary counter with a storage register and 3-state outputs. The storage register has parallel (Q0 to Q7) outputs. The binary counter features master reset counter (MRC) and count enable (CE) inputs. The counter and storage register have separate positive edge triggered clock (CPC and CPR) inputs. If both clocks are connected together, the counter state is always one count ahead of the register. Internal circuitry prevents clocking from the clock enable. A ripple carry output (RCO) is provided for cascading. Cascading is accomplished by connecting RCO of the first stage to CE of the second stage. Cascading for larger count chains can be accomplished by connecting RCO of each stage to the counter clock (CPC) input of the following stage. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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产品详情

特性

Wide supply voltage range from 2.0 V to 6.0 V
CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:

JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)

CMOS input levels
Counter and register have independent clock inputs
Counter has master reset
Multiple package options
ESD protection:

HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

参数类型

Type number	Product status	VCC (V)	Output drive capability (mA)	Logic switching levels	tpd (ns)	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74HC590BQ	Production	2.0 - 6.0	± 5.2	CMOS	19	low	-40~125	88	10.3	56	DHVQFN16
74HC590D	Production	2.0 - 6.0	± 5.2	CMOS	19	low	-40~125	87	7.4	46	SO16
74HC590PW	Production	2.0 - 6.0	± 5.2	CMOS	19	low	-40~125	120	3.4	49.1	TSSOP16