开关/多路复用器/解复用器

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74AHC157-Q100; 74AHCT157-Q100

Quad 2-input multiplexer

应用领域

The 74AHC/AHCT157-Q100 are high-speed Si-gate CMOS devices and are pin compatible with Low Power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

产品详情

The 74AHC/AHCT157-Q100 are quad 2-input multiplexer which select 4 bits of data from two sources under the control of a common data select input (S). The enable input (E) is active LOW. When E is HIGH, all of the outputs (1Y to 4Y) are forced LOW regardless of all other input conditions.

Moving the data from two groups of registers to four common output buses is a common use of the 74AHC/AHCT157-Q100. The state of the common data select input (S) determines the particular register from which the data comes. It can also be used as function generator. The device is useful for implementing highly irregular logic by generating any four of the 16 different functions of two variables with one variable common. The 74AHC/AHCT157-Q100 is logic implementation of a 4-pole, 2-position switch, where the position of the switch is determine by the logic levels applied to S.

The logic equations are:

  • 1Y = E × (1I1 × S + 1I0 × S)

  • 2Y = E × (2I1 × S + 2I0 × S)

  • 3Y = E × (3I1 × S + 3I0 × S)

  • 4Y = E × (4I1 × S + 4I0 × S)

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.


特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Balanced propagation delays

  • All inputs have a Schmitt-trigger action

  • Inputs accepts voltages higher than VCC

  • Multiple input enable for easy expansion

  • Ideal for memory chip select decoding

  • For 74AHC157-Q100 only: operates with CMOS input levels

  • For 74AHCT157-Q100 only: operates with TTL input levels

  • ESD protection:

    • MIL-STD-883, method 3015 exceeds 2000 V

    • HBM JESD22-A114F exceeds 2000 V

    • MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

  • Multiple package options

  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints


参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AHC157BQ-Q100Production2.0 - 5.5CMOS± 83.2low-40~1259112.760DHVQFN16
74AHC157D-Q100Production2.0 - 5.5CMOS± 83.2low-40~125918.950SO16
74AHC157PW-Q100Production2.0 - 5.5CMOS± 83.2low-40~1251234.253TSSOP16
74AHCT157BQ-Q100Production4.5 - 5.5TTL± 83.2low-40~1259112.760DHVQFN16
74AHCT157D-Q100Production4.5 - 5.5TTL± 83.2low-40~125918.950SO16
74AHCT157PW-Q100Production4.5 - 5.5TTL± 83.2low-40~1251234.253TSSOP16