74AUP1G07-Q100

Low-power buffer with open-drain output

应用领域

The 74AUP1G07-Q100 is a single buffer with open-drain output.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 0.8 V to 3.6 V

High noise immunity

CMOS low power dissipation

Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)

JESD8-11 (0.9 V to 1.65 V)

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

ESD protection:

HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 5000 V

MM: JESD22-A115-A exceeds 200 V

MIL-STD-883, method 3015 Class 3A exceeds 5000 V

Low static power consumption; ICC = 0.9 μA (maximum)

Latch-up performance exceeds 100 mA per JESD 78 Class II

Overvoltage tolerant inputs to 3.6 V

Low noise overshoot and undershoot < 10 % of VCC

IOFF circuitry provides partial Power-down mode operation

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74AUP1G07GW-Q100	Production	0.8 - 3.6	CMOS	1.9	70	1	ultra low	-40~125	309	79.2	179	TSSOP5

缓冲器/驱动器/收发器

74AUP1G07-Q100

应用领域

特性

参数类型