74HC2G34-Q100; 74HCT2G34-Q100

Dual buffer gate

应用领域

The 74HC2G34-Q100; 74HCT2G34-Q100 is a dual buffer. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 2.0 V to 6.0 V
High noise immunity
CMOS low power dissipation
Balanced propagation delays
Unlimited input rise and fall times
Input levels:

For 74HC2G34-Q100: CMOS level
For 74HCT2G34-Q100: TTL level

Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards

JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)

ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74HC2G34GV-Q100	Production	2.0 - 6.0	CMOS	± 5.2	36	2	low	-40~125	248	52.7	160	SC-74; TSOP6
74HC2G34GW-Q100	Production	2.0 - 6.0	CMOS	± 5.2	36	2	low	-40~125	275	48.5	163	TSSOP6
74HCT2G34GV-Q100	Production	4.5 - 5.5	TTL	± 4	36	2	low	-40~125	248	52.7	160	SC-74; TSOP6
74HCT2G34GW-Q100	Production	4.5 - 5.5	TTL	± 4	32	2	low	-40~125	275	48.5	163	TSSOP6

缓冲器/驱动器/收发器

74HC2G34-Q100; 74HCT2G34-Q100

应用领域

特性

参数类型