74LV244-Q100

Octal buffer/line driver; 3-state

应用领域

The 74LV244-Q100 is an 8-bit buffer/line driver with 3-state outputs. The device can be used as two 4-bit buffers or one 8-bit buffer. The device features two output enables (1OE and 2OE), each controlling four of the 3-state outputs. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess VCC.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 1.0 to 5.5 V
CMOS low power dissipation
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Optimized for low voltage applications: 1.0 V to 3.6 V
Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V; Tamb = 25 °C
Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V; Tamb = 25 °C
Complies with JEDEC standards:

JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)

ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74LV244D-Q100	Production	1.0 - 5.5	CMOS	± 16	30	8	low	-40~125	76	19.1	52	SO20
74LV244PW-Q100	Production	1.0 - 5.5	CMOS	± 16	30	8	low	-40~125	94	3.1	38.3	TSSOP20

缓冲器/驱动器/收发器

74LV244-Q100

应用领域

特性

参数类型