74LVC16245A-Q100; 74LVCH16245A-Q100

16-bit bus transceiver with direction pin; 5 V tolerant; 3-state

应用领域

The 74LVC16245A-Q100; 74LVCH16245A-Q100 is a 16-bit transceiver with 3-state outputs. The device can be used as two 8-bit transceivers or one 16-bit transceiver. The device features two output enables (1OE and 2OE) each controlling eight outputs, and two send/receive (1DIR and 2DIR) inputs for direction control. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use i

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power dissipation
MULTIBYTE flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold (74LVCH16245A-Q100 only)
IOFF circuitry provides partial Power-down mode operation
Complies with JEDEC standard:

JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)

ESD protection:

MIL-STD-883, method 3015 exceeds 2000V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
CDM ANSI/ESDA/Jedec JS-002 exceeds 1000 V

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74LVC16245ADGG-Q100	Production	1.2 - 3.6	CMOS/LVTTL	+/- 24	175	16	low	-40~125	82	1.9	36	TSSOP48
74LVC16245ADGV-Q100	Production	1.2 - 3.6	CMOS/LVTTL	+/- 24	175	16	low	-40~125	82	0.0	36	TVSOP48
74LVCH16245ADGG-Q100	Production	1.2 - 3.6	CMOS/LVTTL	+/- 24	175	16	low	-40~125	82	1.9	36	TSSOP48
74LVCH16245ADGV-Q100	Production	1.2 - 3.6	CMOS/LVTTL	+/- 24	175	16	low	-40~125	82	0.0	36	TVSOP48

缓冲器/驱动器/收发器

74LVC16245A-Q100; 74LVCH16245A-Q100

应用领域

特性

参数类型