74LVC3G04-Q100

Triple inverter

应用领域

The 74LVC3G04-Q100 is a triple inverter. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)

ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)

±24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name code identifying a defacto industry term for a package type
74LVC3G04DC-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 32	175	3	low	-40~125	205	35.5	115	VSSOP8
74LVC3G04DP-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 32	175	3	low	-40~125	217	20.7	106	TSSOP8

缓冲器/驱动器/收发器

74LVC3G04-Q100

应用领域

特性

参数类型