74AVC1T45-Q100

Dual-supply voltage level translator/transceiver; 3-state

应用领域

The 74AVC1T45-Q100 is a single bit, dual supply transceiver with 3-state output that enables bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to VCC(A) and pin B is referenced to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission from B to A.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.

This product has been qualified to the Aut

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range:

VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V

High noise immunity
CMOS low power dissipation
Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)
JESD8-11( 0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)

ESD protection:

MIL-STD-883, method 3015 Class 3B exceeds 8000 V
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)

Maximum data rates:

500 Mbit/s (1.8 V to 3.3 V translation)
320 Mbit/s (< 1.8 V to 3.3 V translation)
320 Mbit/s (translate to 2.5 V or 1.8 V)
280 Mbit/s (translate to 1.5 V)
240 Mbit/s (translate to 1.2 V)

Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Dynamically controlled outputs
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options

参数类型

Type number	Product status	VCC(A) (V)	VCC(B) (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74AVC1T45GM-Q100	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	2.1	1	very low	-40~125	286	6.3	142	XSON6
74AVC1T45GS-Q100	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	2.1	1	very low	-40~125	262	12.2	170	XSON6
74AVC1T45GW-Q100	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	2.1	1	very low	-40~125	262	36.1	150	TSSOP6

逻辑电压转换器

74AVC1T45-Q100

应用领域

特性

参数类型