74AVC8T245-Q100

8-bit dual supply translating transceiver with configurable voltage translation; 3-state

应用领域

The 74AVC8T245-Q100 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two 8-bit input-output ports (An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or V

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range: VCC(A): 0.8 V to 3.6 V; VCC(B): 0.8 V to 3.6 V
Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)

ESD protection:

MIL-STD-883, method 3015 class 3B exceeds 8000 V
HBM JESD22-A114E class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

Maximum data rates:

380 Mbit/s (≥ 1.8 V to 3.3 V translation)
260 Mbit/s (≥ 1.1 V to 3.3 V translation)
260 Mbit/s (≥ 1.1 V to 2.5 V translation)
210 Mbit/s (≥ 1.1 V to 1.8 V translation)
150 Mbit/s (≥ 1.1 V to 1.5 V translation)
100 Mbit/s (≥ 1.1 V to 1.2 V translation)

Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

参数类型

Type number	Product status	VCC(A) (V)	VCC(B) (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74AVC8T245BQ-Q100	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	2.1	8	very low	-40~125	67	6.2	41	DHVQFN24
74AVC8T245PW-Q100	Production	0.8 - 3.6	0.8 - 3.6	CMOS/LVTTL	± 12	2.1	8	very low	-40~125	81	2.3	36	TSSOP24

逻辑电压转换器

74AVC8T245-Q100

应用领域

特性

参数类型