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8-bit dual supply translating transceiver; 3-state
The 74LVC8T245-Q100; 74LVCH8T245-Q100 are 8-bit dual supply translating transceivers with 3-state outputs that enable bidirectional level translation. They feature two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 1.2 V and 5.5 V. This flexibility makes the device suitable for translating between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.
The devices are fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
VCC(A): 1.2 V to 5.5 V
VCC(B): 1.2 V to 5.5 V
High noise immunity
Complies with JEDEC standards:
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)
JESD36 (4.5 V to 5.5 V)
ESD protection:
MIL-STD-883, method 3015 Class 3A exceeds 4000 V
HBM JESD22-A114F Class 3A exceeds 4000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Maximum data rates:
420 Mbps (3.3 V to 5.0 V translation)
210 Mbps (translate to 3.3 V))
140 Mbps (translate to 2.5 V)
75 Mbps (translate to 1.8 V)
60 Mbps (translate to 1.5 V)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78B Class II
±24 mA output drive (VCC = 3.0 V)
Inputs accept voltages up to 5.5 V
Low power consumption: 30 μA maximum ICC
IOFF circuitry provides partial Power-down mode operation
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
| Type number | Product status | VCC(A) (V) | VCC(B) (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC8T245BQ-Q100 | Production | 1.2 - 5.5 | 1.2 - 5.5 | CMOS/LVTTL | ± 24 | 3.5 | 8 | low | -40~125 | 66 | 5.8 | 40 | DHVQFN24 |
| 74LVC8T245PW-Q100 | Production | 1.2 - 5.5 | 1.2 - 5.5 | CMOS/LVTTL | ± 24 | 3.5 | 8 | low | -40~125 | 81 | 2.3 | 36 | TSSOP24 |
| 74LVCH8T245BQ-Q100 | Production | 1.2 - 5.5 | 1.2 - 5.5 | CMOS/LVTTL | ± 24 | 3.5 | 8 | low | -40~125 | 66 | 5.8 | 40 | DHVQFN24 |
| 74LVCH8T245PW-Q100 | Production | 1.2 - 5.5 | 1.2 - 5.5 | CMOS/LVTTL | ± 24 | 3.5 | 8 | low | -40~125 | 81 | 2.3 | 36 | TSSOP24 |
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