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Quad 2-input NAND gate
The 74ALVC00-Q100 is a quad 2-input NAND gate.
Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications.
Automotive product qualification in accordance with AEC-Q100 (Grade 3)
Specified from -40 °C to +85 °C
Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B (2.7 V to 3.6 V)
ESD protection:
MM JESD22-A115-A exceeds 200 V
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1 kV
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
| Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) operating thermal resistance between the junction and ambient free air of an electric-electronic component | Ψth(j-top) (K/W) operating thermal characterization parameter measured between the junction and top center of a package of an integrated circuit component | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVC00BQ-Q100 | Production | 1.65 - 3.6 | TTL | ± 24 | 2.1 | 145 | 4 | low | -40~85 | 103 | 18.3 | 71 | DHVQFN14 |
| 74ALVC00D-Q100 | Production | 1.65 - 3.6 | TTL | ± 24 | 2.1 | 145 | 4 | low | -40~85 | 103 | 17.1 | 62 | SO14 |
| 74ALVC00PW-Q100 | Production | 1.65 - 3.6 | TTL | ± 24 | 2.1 | 145 | 4 | low | -40~85 | 138 | 6.9 | 64 | TSSOP14 |
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