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Quad 2-input OR gate with Schmitt trigger inputs
The 74LV7032A-Q100 is a quad 2-input OR function with Schmitt-trigger inputs, capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
Inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments.
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 2.0 V to 5.5 V
Maximum tpd of 9.5 ns at 5 V
Typical VOL(p)< 0.8 V at VCC = 3.3 V, Tamb = 25 °C
Typical VOH(v)> 2.3 V at VCC = 3.3 V, Tamb = 25 °C
Supports mixed-mode voltage operation on all ports
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA per JESD 78 Class II
ESD protection:
MM: MM JESD22-A115-B exceeds 200 V
HBM: ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4 kV
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 2 kV
| Type number | Product status | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV7032APW-Q100 | Production | CMOS | ± 12 | 4.3 | 45 | 4 | low | -40~125 | 140 | 7.5 | 66 | TSSOP14 |
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