Quad 2-input NAND gate
The 74LVC00A-Q100 is a quad 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Overvoltage tolerant inputs to 5.5 V
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low-power consumption
Direct interface with TTL levels
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)
Multiple package options
DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints
Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74LVC00ABQ-Q100 | Production | 1.2 - 3.6 | CMOS/LVTTL | ± 24 | 2.1 | 150 | 4 | low | -40~125 | 109 | 23.4 | 77 | DHVQFN14 |
74LVC00AD-Q100 | Production | 1.2 - 3.6 | CMOS/LVTTL | ± 24 | 2.1 | 150 | 4 | low | -40~125 | 112 | 22.6 | 70 | SO14 |
74LVC00APW-Q100 | Production | 1.2 - 3.6 | CMOS/LVTTL | ± 24 | 2.1 | 150 | 4 | low | -40~125 | 144 | 8.7 | 70 | TSSOP14 |