74LVC2G08-Q100

Dual 2-input AND gate

应用领域

The 74LVC2G08-Q100 is a dual 2-input AND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

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产品详情

特性

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
Overvoltage tolerant inputs to 5.5 V
IOFF circuitry provides partial Power-down mode operation
High noise immunity
±24 mA output drive (VCC = 3.0 V)
CMOS low power dissipation
Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)

Latch-up performance exceeds 250 mA
Direct interface with TTL levels
ESD protection:

MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

Multiple package options

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74LVC2G08DC-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 24	2.1	150	2	low	-40~125	200	32.4	110	VSSOP8
74LVC2G08DP-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 24	2.1	150	2	low	-40~125	210	18.8	104	TSSOP8
74LVC2G08GS-Q100	Production	1.65 - 5.5	CMOS/LVTTL	± 24	2.1	150	2	low	-40~125	269	9.7	141	XSON8

门

74LVC2G08-Q100

应用领域

特性

参数类型