Quad 2-input NOR gate
The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.
Balanced propagation delays
All inputs have a Schmitt-trigger action
Inputs accept voltages higher than VCC
Input levels:
For 74AHC02: CMOS level
For 74AHCT02: TTL level
ESD protection:
HBM EIA/JESD22-A114E exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101C exceeds 1000 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Type number | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Nr of bits | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74AHC02BQ | Production | 2.0 - 5.5 | CMOS | ± 8 | 2.9 | 60 | 4 | low | -40~125 | 103 | 18.4 | 71 | DHVQFN14 |
74AHC02D | Production | 2.0 - 5.5 | CMOS | ± 8 | 2.9 | 60 | 4 | low | -40~125 | 105 | 17.8 | 63 | SO14 |
74AHC02PW | Production | 2.0 - 5.5 | CMOS | ± 8 | 2.9 | 60 | 4 | low | -40~125 | 138 | 6.9 | 64 | TSSOP14 |
74AHCT02BQ | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 60 | 4 | low | -40~125 | 103 | 18.4 | 71 | DHVQFN14 |
74AHCT02D | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 60 | 4 | low | -40~125 | 105 | 17.8 | 63 | SO14 |
74AHCT02PW | Production | 4.5 - 5.5 | TTL | ± 8 | 3.8 | 60 | 4 | low | -40~125 | 138 | 1.0 | 8 | TSSOP14 |