74ALVC02

Quad 2-input NOR gate

应用领域

The 74ALVC02 is a quad 2-input NOR gate.

Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

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产品详情

特性

Wide supply voltage range from 1.65 V to 3.6 V
CMOS low power dissipation
Overvoltage tolerant inputs to 3.6 V
Direct interface with TTL levels
IOFF circuitry provides partial Power-down mode operation
Latch-up performance exceeds 250 mA per JESD78 Class II.A
Complies with JEDEC standards:

JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C/JESD36 (2.7 V to 3.6 V)

ESD protection:

HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1 kV

Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74ALVC02BQ	Production	1.65 - 3.6	TTL	± 24	2.2	150	4	low	-40~85	103	18.3	71	DHVQFN14
74ALVC02D	Production	1.65 - 3.6	TTL	± 24	2.2	150	4	low	-40~85	103	17.1	62	SO14
74ALVC02PW	Production	1.65 - 3.6	TTL	± 24	2.2	150	4	low	-40~85	138	1.0	64	TSSOP14

门

74ALVC02

应用领域

特性

参数类型