74ALVC08

Quad 2-input AND gate

应用领域

The 74ALVC08 is a quad 2-input AND gate. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times.

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产品详情

特性

Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:

JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B (2.7 V to 3.6 V)

ESD protection:

MM JESD22-A115-A exceeds 200 V
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1 kV

ESD protection:

MM JESD22-A115-A exceeds 200 V
HBM JESD22-A114E exceeds 2000 V

Multiple package options
Specified from -40 °C to +85 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74ALVC08BQ	Production	1.65 - 3.6	TTL	± 24	2.0	150	4	low	-40~85	103	18.3	71	DHVQFN14
74ALVC08D	Production	1.65 - 3.6	TTL	± 24	2.0	150	4	low	-40~85	103	17.1	62	SO14
74ALVC08PW	Production	1.65 - 3.6	TTL	± 24	2.0	150	4	low	-40~85	138	6.9	64	TSSOP14

门

74ALVC08

应用领域

特性

参数类型