74AUP1G3208

Low-power 3-input OR-AND gate

应用领域

The 74AUP1G3208 is a single 3-input OR-AND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

附件下载立即咨询在线申请

产品详情

特性

Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Complies with JEDEC standards:

JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8C (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114F Class 3A exceeds 5000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V

Low static power consumption; ICC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD 78 Class II
Overvoltage tolerant inputs to 3.6 V
Low noise overshoot and undershoot < 10 % of VCC
IOFF circuitry provides partial Power-down mode operation
Multiple package options
Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	fmax (MHz)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74AUP1G3208GM	Production	0.8 - 3.6	CMOS	± 1.9	7.4	70	1	ultra low	-40~125	290	6.5	145	XSON6
74AUP1G3208GN	Production	0.8 - 3.6	CMOS	± 1.9	7.4	70	1	ultra low	-40~125	275	11.7	171	XSON6
74AUP1G3208GS	Production	0.8 - 3.6	CMOS	± 1.9	7.4	70	1	ultra low	-40~125	272	14.8	177	XSON6
74AUP1G3208GW	Production	0.8 - 3.6	CMOS	± 1.9	7.4	70	1	ultra low	-40~125	264	38.6	153	TSSOP6
74AUP1G3208GX	Production	0.8 - 3.6	CMOS	± 1.9	7.4	70	1	ultra low	-40~125	-	-	-	X2SON6

门

74AUP1G3208

应用领域

特性

参数类型