奇偶生成器/校验器

汽车逻辑器件同步接口逻辑器件控制逻辑器件开关二极管 N沟道MOS管三级管

74HC280; 74HCT280

9-bit odd/even parity generator/checker

应用领域

The 74HC280; 74HCT280 is a 9-bit parity generator or checker. Both even and odd parity outputs are available. The even parity output (PE) is HIGH when an even number of data inputs (I0 to I8) is HIGH. The odd parity output (PO) is HIGH when an odd number of data inputs are HIGH. Expansion to larger word sizes is accomplished by tying the even outputs (PE) of up to nine parallel devices to the final stage data inputs. Inputs include clamp diodes. It enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

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产品详情

特性

Word-length easily expanded by cascading
Generates either odd or even parity for nine data bits
Wide supply voltage range from 2.0 to 6.0 V
Input levels:

For 74HC280: CMOS level
For 74HCT280: TTL level

CMOS low power dissipation
High noise immunity
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards

JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)

ESD protection:

HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V

Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74HC280D	Production	2.0 - 6.0	CMOS	± 5.2	17	low	-40~125	73	1.0	30	SO14
74HCT280D	Production	4.5 - 5.5	TTL	± 4	18	low	-40~125	76	1.0	34	SO14
74HCT280PW	Production	4.5 - 5.5	TTL	± 4	18	low	-40~125	-	-	-	TSSOP14