74ALVC373

Octal D-type transparent latch; 3-state

应用领域

The 74ALVC373 is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

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产品详情

特性

Wide supply voltage range from 1.65 V to 3.6 V
3.6 V tolerant inputs/outputs
CMOS low power consumption
Direct interface with TTL levels (2.7 V to 3.6 V)
Power-down mode
Latch-up performance exceeds 250 mA
Complies with JEDEC standards:

JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B (2.7 V to 3.6 V)

ESD protection:

MM JESD22-A115-A exceeds 200 V
HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV
CDM ANSI/ESDA/JEDEC JS-002 Class C3 exceeds 1 kV

ESD protection:

HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V

Multiple package options
Specified from -40 °C to +85 °C

参数类型

Type number	Product status	VCC (V)	Logic switching levels	Output drive capability (mA)	tpd (ns)	Nr of bits	Power dissipation considerations	Tamb (°C)	Rth(j-a) (K/W)	Ψth(j-top) (K/W)	Rth(j-c) (K/W)	Package name
74ALVC373BQ	Production	1.65 - 3.6	LVTTL	± 24	2.2	8	low	-40~85	77	8.4	49	DHVQFN20
74ALVC373D	Production	1.65 - 3.6	LVTTL	± 24	2.2	8	low	-40~85	84	26.7	60	SO20
74ALVC373PW	Production	1.65 - 3.6	LVTTL	± 24	2.2	8	low	-40~85	100	4.5	44.2	TSSOP20

锁存器/寄存驱动器

74ALVC373

应用领域

特性

参数类型