锁存器/寄存驱动器

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74HC75

Quad bistable transparant latch

应用领域

The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEnn is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEnn will be stored in the latches. The latched outputs remain stable as long as the LEnn is LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

产品详情

特性

  • Wide supply voltage range from 2.0 V to 6.0 V

  • CMOS low power dissipation

  • High noise immunity

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • Complies with JEDEC standards:

    • JESD8C (2.7 V to 3.6 V)

    • JESD7A (2.0 V to 6.0 V)

  • Complementary Q and Q outputs

  • VCC and GND on the center pins

  • CMOS input levels

  • ESD protection:

    • HBM EIA/JESD22-A114F exceeds 2000 V

    • MM EIA/JESD22-A115-A exceeds 200 V

  • Specified from -40 °C to +80 °C and from -40 °C to +125 °C.


参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74HC75DProduction2.0 - 6.0CMOS± 5.2114low-40~125772.635SO16
74HC75PWProduction2.0 - 6.0CMOS± 5.2114low-40~1251111.439TSSOP16